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4-55

SIMATIC 545/555/575 System Manual

Installing 575 System Hardware

When using the 575 CPU and third-party boards, you must be aware of the

following limitations.

• The 575 CPU VMEbus data strobe timeout is 40 microseconds. The

third-party VMEbus boards must respond to a 575 request in less than

40 microseconds or VMEbus error occurs. Unless the MOVE instruction

was used, this causes a fatal error.

• VMEbus block transfers are not supported. Third-party boards may not

use VMEbus block transfers to or from the CPU shared memory. All

data transfers must be accomplished by VMEbus word or byte

read/write.

• The 575 CPU reserves Address Modifier 2D

address 122

. Any

attempt to access this address (Read, Write, Read/Modify/Write or

address-only cycle) results in disabling the 575 VMEbus I/O module

outputs.

• The 575 CPU does not perform D32 VMEbus cycles, nor allow D32

VMEbus cycles to or from CPU shared memory. Long word

Read/Modify/Write operations are not indivisible across the backplane.

The Motorolar 68K CAS.L and CAS2 instructions should not have

destinations on the VMEbus.

• The 575 CPU implements the Read-Modify-Write (RMW) cycle by

maintaining control of the VMEbus by using the BBSY signal. This

precludes the use of semaphores residing on dual-ported memory on a

third-party master if the third-party master does not acquire the

VMEbus first, before accessing its dual-ported memory.

• Read and write operations to the Global Configuration Status Registers

in the VMEbus short supervisory address space (VMEbus address

modifier 2D

) must be limited to byte transfers on odd addresses only.

The GCSR is a D08(O) slave. Do not use word or long word read or

write operations to access Global Configuration Status Registers. If

these operations are performed, a VMEbus error occurs.

• Accesses (also address-only bus cycles) to VMEbus short supervisory

space (VMEbus address modifier 2D

) addresses A16_Base_Address +

(F0

...F7

) must be avoided. If these operations are performed, the

575 CPUs in the system waste time servicing an unsupported location

monitor interrupt.

Table 4-7 lists the signal mnemonics assigned to each pin in the J1

backplane connector, as defined by the VMEbus standard.

VMEbus Access

Limitations

1 2 ... 133 134 135 136 137 138 139 140 141 142 143 ... 321 322

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