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16-7

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write x x x x – x x x 1

I 0.0

A signal state of 1 at input I 0.0 activates the

instruction.

Memory double word MD0 is shifted to the right

by the number of bits specified in memory word

MW4.

The result is put into MD10. If the signal state of

the bit shifted last was 1, output Q 4.0 is set.

Q 4.0

SHR_DW

OUT

MW4

Function is executed (EN = 1):

MD10

MD0

EN ENO

Figure 16-5 Shift Right Double Word

A signal state of 1 at the Enable (EN) input activates the Shift Right Integer

instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the

right. Input N specifies the number of bits by which to shift. If N is larger

than 16, the command behaves as if N were 16. The bit positions at the left

are padded according to the signal state of bit 15 (which is the sign of an

integer number), that is, they are filled with zeros if the number is positive,

and with ones if it is negative. The result of the shift operation can be

scanned at output OUT.

The operation triggered by this instruction always resets the CC 0 and OV

bits of the status word to 0. If the box is executed (EN = 1), ENO shows the

signal state of the bit shifted last (same as CC 1 and RLO in the status word).

The result is that other functions following this box that are connected by the

ENO (cascade arrangement) are not executed if the bit shifted last had a

signal state of 0.

Certain restrictions apply to the placement of the Shift Right Integer box (see

Section 6.1).

Shift Right Integer

Shift and Rotate Instructions

1 2 ... 206 207 208 209 210 211 212 213 214 215 216 ... 317 318

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Siemens NAN 67 Series Manual de servicio Pagina 211