Siemens NAN 67 Series Manual de servicio descargar pdf (Pagina 118)

8-20

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

8.19 Negative RLO Edge Detection

The operation Negative RLO Edge Detection recognizes a change in the

entered address from 1 to 0 (falling edge) and displays this as RLO = 1 after

the operation. The current signal state in the RLO is compared with the

signal state of the address, the edge memory bit. If the signal state of the

address is 1 and the RLO was 0 before the operation, the RLO will be 0

(impulse) after the operation, and 1 in all other cases. The RLO prior to the

operation is stored in the address.

Certain restrictions apply to the placement of the Negative RLO Edge

Detection element (see Section 6.1).

Table 8-18 Negative RLO Edge Detection Element and Parameter

LAD Element Parameter Data Type Memory Area Description

<address1> BOOL Q, M, D

The address indicates the edge memory

bit that stores the previous RLO.

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write – – – – – x x x 1

I 0.0 CAS1

Edge memory bit M 0.0 saves the old

state of the RLO from the complete bit

logic combination. If there is a signal

change at the RLO from 1 to 0, the

program jumps to label CAS1.

I 0.2

I 0.1

N JMP

M 0.0

Figure 8-18 Negative RLO Edge Detection

Description

Bit Logic Instructions

1 2 ... 113 114 115 116 117 118 119 120 121 122 123 ... 317 318

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