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8-18

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

8.17 Off-Delay Timer Coil

The Off-Delay Timer Coil (SF) instruction starts a specified timer if the RLO

has a negative edge (that is, a transition from 1 to 0 takes place in the RLO).

The result of a signal state check of the timer number for 1 is 1 when the

RLO is 1, or when the timer is running. The timer is reset when the RLO

goes from 0 to 1 while the timer is running. The timer is not restarted until

the RLO changes from 1 to 0.

For information on the location of a timer in memory and the components of

a timer, see Section 9.1.

Table 8-16 Off-Delay Timer Coil Element and Parameters, with SIMATIC and International Short Name

LAD Element

Parameter Data Type Memory Area Description

Timer

number

TIMER T The address indicates the number

of the timer that is to be started.

Time value

Time value S5TIME I, Q, M, D, L Time value (S5TIME format)

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write – – – – – 0 – – 0

I 0.0 T 5

If the signal state of input I 0.0 changes from 1

to 0, the timer is started.

If the signal state of I 0.0 changes from 0 to 1,

the timer is reset.

The signal state of output Q 4.0 is 1 when the

signal state of input I 0.0 is 1, or when the

timer is running.

T 5 Q 4.0

S5T# 2s

Figure 8-16 Off-Delay Timer Coil

Description

Parameters

Bit Logic Instructions

1 2 ... 111 112 113 114 115 116 117 118 119 120 121 ... 317 318

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