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8-24

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

8.23 Reset Set Flipflop

The Reset Set Flipflop instruction executes Set (S) and Reset (R) operations

only when the RLO is 1. An RLO of 0 has no effect on these operations; the

address specified in the operation remains unchanged.

A Reset Set Flipflop is reset if the signal state is 1 at the R input and 0 on the

S input. Otherwise, if the signal state is 0 at the R input and 1 at the S input,

the Flipflop is set. If the RLO is 1 at both inputs, the Flipflop is set.

The Reset Set Flipflop instruction is affected by the Master Control Relay

(MCR). For more information on how the MCR functions, see Section 20.5.

Certain restrictions apply to the placement of the Reset Set Flipflop box (see

Section 6.1).

Table 8-22 Reset Set Flipflop Box and Parameters

LAD Box

Parameter Data Type Memory Area Description

<address> BOOL I, Q, M, D, L

The address indicates the bit that is to be

set or reset.

R BOOL I, Q, M, D, L Enabled reset operation

S BOOL I, Q, M, D, L Enabled set operation

Q BOOL I, Q, M, D, L Signal state of <address>

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write – – – – – x x x 1

I 0.0

If the signal state is 1 at input I 0.0 and 0

at input I 0.1, memory bit M 0.0 is reset,

and output Q 4.0 is 0.

Otherwise, if the signal state is 0 at input

I 0.0 and 1 at input I 0.1, memory bit

M 0.0 is set and Q 4.0 is 1.

If both signal states are 0, nothing is

changed. If both signal states are 1, the

Set operation dominates because of the

order, M 0.0 is set, and Q 4.0 is 1.

Q 4.0

M 0.0

I 0.1

Figure 8-22 Reset Set Flipflop

Description

Bit Logic Instructions

1 2 ... 117 118 119 120 121 122 123 124 125 126 127 ... 317 318

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