
9-14
Ladder Logic (LAD) for S7-300 and S7-400
C79000-G7076-C504-02
Figure 9-7 shows the Off-Delay S5 Timer instruction, describes the status
word bits, and shows the pulse timer characteristics.
If the signal state of input I 0.0 changes from 1 to 0
(that is, there is a negative edge in the RLO), the
timer is started. The signal state of output Q 4.0 is 1
when the signal state of I 0.0 is 1 or the timer is
running (see also Section 9.3). If the signal state of
input I 0.1 changes from 0 to 1 while the timer is
running, the timer is reset.
Status Word Bits
BR CC 1 CC 0 OV OS OR STA RLO FC
Write – – – – – x x x 1
Timing Diagram
RLO at S input
RLO at R input
Timer running
Signal state check for 1
Signal state check for 0
t = programmed time
–– t –– –– t ––
I 0.0
T 5
S_OFFDT
R
Q
TV BI
BCD
S5T# 2s
I 0.1
Q 4.0
S
Figure 9-7 Off-Delay S5 Timer
Example
Timer Instructions
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