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Addressing

3-3

ET 200S IM 151-7 CPU Interface Module

A5E00058783-04

Address Assignment

Depending on the slot, 1 byte is reserved for digital I/Os and 16 bytes are reserved

for analog I/Os in the address areas of the IM 151/7 CPU for each I/O module

(maximum of 63).

The table below indicates the default address assignment for analog and digital

modules per slot. The address areas of the I/O modules are ”visible” only to an

IM 151-7 CPU in the ET 200S, not to the associated DP master. The DP master

has no direct access to the I/O modules.

Table 3-1 Addresses of the ET 200S I/O modules

Reserved

Slot Number

Address Area

1 2 3 4 5 6 7 8 ... 66

Digital

modules, motor

starters

- 1 2 3 4 ... 62

Analog

modules,

process-related

modules

151-7 CPU*

IM 151-7 CPU

151-7 CPU*

- 272 to

287

288 to

303

304 to

319

320 to

335

... 1248 to

1263

Power modules

256 272 288 304 320 1248

* With X1 as the MPI-/DP interface and X2 as the DP master interface

The unassigned addresses in the range 64 to 127 are in the process image in

default addressing and can be used any way you choose in the user program. If 2

bits in a byte are already occupied by a digital module, the remaining 6 bits cannot

be used as you choose (e.g. the bits 1.4 to 1.7 in Figure 3-3).

You can use the bytes in the address areas that are not used by modules in any

way you choose in your user program. In the configuration in Figure 3-3, for

example, bytes 2 and 3 can be used as you choose.

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 213 214

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