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Response Times IP 240
12.3 Firmware Execution Times
The execution time of the individual firmware slices depends on
• the modes in which the channels are operated,
• the configuring data and
• the current actual value.
The table below shows the
• base times which the firmware needs in each cycle to process channel 1 and channel 2.
• the additional times needed only in the firmware cycle in which the setpoint is reached or in
which an error occurs.
• the execution time for a data interchange in the relevant mode.
When computing the response time, you must always assume the maximum value for a data inter-
change.
Position decoding mode
Table 12-1. Firmware Execution Times, Position Decoding Mode
Description
Base time without configuring 45 µs
Abbrev.
Max. execu-
tion time
t
A
Base time for position decoding without track comparison
Base time per track comparison without hysteresis
Base time per track comparison with hysteresis
Additional time for entering and exiting a track
Additional time for IP 240 to set or reset an output (per DQ)
Additional time for IP 240 to generate an interrupt
(for each interrupt bit set)
Time for a data exchange
Data Read
Data Write
t
WS1
t
WS2
t
W
520 µs
160 µs
230 µs
t
WZ1
30 µs
t
WZ2
45 µs
t
WZ3
30 µs
t
kom
t
kom
430 µs
740 µs
Example:
Channel 1: • Base time without configuring t
A
= 45 µs
• Position decoding modes t
W
= 520 µs
• 6 tracks used, without hysteresis 6 x t
WS1
= 960 µs
In one FW cycle,
• a track can be entered, t
WZ1
= 30 µs
• an output set and
the other output reset and 2 x t
WZ2
= 90 µs
• an actual value-dependent interrupt generated. t
WZ3
= 30 µs
----------------
t
ka1
= 1675 µs
12-4
EWA 4NEB 811 6120-02a
- SIMATIC S5 1
- Counter/Positioning/ 1
- Position Decoder Module 1
- Copyright © Siemens AG 1990 2
- First Printing, March 1991 2
- EWA 4NEB 811 6120-02c 3
- IP 240 Preface 5
- Introduction 6
- Introduction IP 240 7
- Conventions 10
- EWA 4NEB 811 6120-02a 11
- 1 System Overview 13
- System Overview 14
- 2.2 Technical Specifications 18
- 2.2.2 Counting 19
- 2.2.3 Inputs/Outputs 20
- 2.3 LEDs 23
- 2.4 Order Numbers 24
- 3 Addressing 27
- Addressing IP 240 28
- IP 240 Addressing 29
- 4 Hardware Installation 32
- 4.2 Wiring 35
- 4.2.1 Wiring Method 35
- 4.3 Installation Examples 38
- 4.3.1 Inputs 38
- 4.3.2 Outputs 43
- ((1887/3)) 43
- 6.1.2 Digital Outputs 56
- 6.1.3 Interrupt generation 56
- 6.1.4 LEDs 56
- 6.2 Programming 57
- 6.2.2 Control Function Blocks 58
- 6.2.3 Data Blocks 58
- 6.3 Restart Characteristics 59
- 6.3.1 Power On 59
- 6.3.2 CPU STOP 59
- 6.4 Fault and Error Flagging 59
- 6.5 Multiprocessor Operation 62
- 7 Position Decoding 65
- 7.2.2 Resolution 67
- 7.2.3 Reference Tracks 68
- 7.2.4 Hysteresis 73
- 7.2.5 Forcing the IP Outputs 77
- 7.3.2 Control Function Block 87
- 67: KH = 7450; 99
- Position Decoding IP 240 100
- IP 240 Position Decoding 101
- 8 Counting 126
- Counting IP 240 127
- 8.2.2 Final Value 128
- 8.2.3 Forcing the IP Output 128
- IP 240 Counting 130
- 8.3.2 Control Function Block 136
- 9 IP 252 Expansion 156
- IP 252 Expansion IP 240 157
- IP 240 IP 252 Expansion 158
- YOU must 159
- 9.4.2 Data Block Contents 162
- 10 Positioning 167
- 10.1.2 Functional Description 168
- IP 240 Positioning 169
- Positioning IP 240 170
- Switching the IP outputs 173
- 10.3 Numerical Representation 176
- - Actual value 178
- 10.4 Axis Types 180
- 10.4.1 Linear Axis 180
- 10.4.2 Rotary Axis 181
- 10.5 Switching the IP Outputs 183
- 10.7 Actual Value Generation 189
- 10.7.1 Resolution (AFL) 190
- · Specified resolution 191
- 10.7.2 Zero Offset 192
- A negative value must be spe 194
- = - 2,000 194
- a 214
- 10.14 Selecting a Position 216
- 10.14.2 Selecting Position 0 218
- DR n+3 231
- : JU FB 168 232
- 10.23.1 The Data Block 241
- DW 32 to 242
- = 0 Relative zero offset 248
- • Actual value 253
- Format Description 258
- Exceeding 255 260
- With offset 15 you address: 297
- 11.1.1 Status Register 298
- Read error codes 300
- IDLE=1? 301
- 11.4.1 Position Decoding Mode 306
- 11.4.2 Counting Mode 310
- 11.4.3 Reading Error Messages 313
- 11.5 Sample Programs 314
- 12 Response Times 321
- Response Times IP 240 322
- IP 240 Response Times 323
- 12.3 Firmware Execution Times 324
- 13 Encoder Signals 329
- 13.1.2 Timing Requirements 330
- IP 240 Encoder Signals 331
- Encoder Signals IP 240 332
- EWA 4NEB 811 6120-02 a 335
- 14 Error Messages 337
- Invalid hysteresis 338
- 14.2.2 Communications Errors 339
- 14.4.1 Parameter Errors 339
- 14.4.2 Data Errors 340
- =02 Error on selecting HASY 341
- 14.4.3 Communications Errors 342
- Adapter Casing (S5 Adapter) 343
- A.1 Prerequisites 344
- A.4 Interrupt Processing 347
- A.5 Technical Specifications 348
- Addressing S5 Modules 349
- (Adapter Casing and IM 463-2) 349
- B.1 Addressing S5 Modules 350
- I/O area (P area) 351
- Page area 351
- Positioning Module 353
- C.1 Overview 354
- Example: 355
- Standard functions: 355
- Examples: 355
- C.2 Counting Functions 356
- Function FC 171 (STRU_DOS) 356
- Function FC 172 (STEU_DOS) 357
- EWA 4NEB 811 6120-02b 358
- Function FC 164 (STRU_WEG) 359
- Function FC 170 (STEU_WEG) 360
- C.4 Positioning Functions 362
- Function FC 167 (STRU_POS) 362
- Function FC 168 (STEU_POS) 363
- Addresses 368
- Cyclic Program 370
- Interrupt Program 371
- DB 170.DBB 45 Hysteresis 377
- IP 240 Index 388
- Index IP 240 389
- 6-1, 10-12, 10-13 393
- 6-1, 7-1 ... 7-3, 7-5 397
- EWA 4NEB 811 6120-02 398
- 5 Operation 409
- 5.1.1 IRx Interrupt Circuits 410
- 5.1.2 I/O Byte 0 (PY) 411
- Master or Slave 412
- Enable for I/O byte 0 412
- IP 240 Operation 413
- 5.2 Output Inhibit (BASP) 414
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