Siemens IP-Module Especificaciones descargar pdf (Pagina 129)

100

101

Counting IP 240

The following options are available for forcing the output:

a) The digital output is to be set when the actual value reaches ”0”, and reset on the first pos-

itive GATE signal edge following the start of a new count.

In this case, you must set control bits DA1F to 0 and DA1S to 1 in DL 17.

b) The digital output is to be reset without regard to the count.

In this case, you must set control bits DA1F to 0 and DA1S to 0.

c) The digital output is to be set without regard to the count.

In this case, you must set control bits DA1F to 1 and DA1S to 1.

It is important to note that after transferring the control bits DA1f=1 and DA1s=1, the

IP output D1 is to be reset by transferring the control bits DA1F=0 and DA1S=0, before the

output control can be selected according to a) (DA1F=0 and DA1F=1)

Status bit DA1 mirrors the current state of the output.

Figure 8-2 shows an example of triggering a process interrupt and activating the digital output.

Fig. 8-2. Sequence Diagram for Counting Mode

CLOCK signal

REF1 triggers an interrupt

1) These bits are reset on the IP following reading of the status area.

2) The interrupt request is reset when the interrupt request bytes are read.

3) This edge is no longer counted, as the GATE signal was set to ”0”.

3 2 1 0 -1 -1

GATE signal

IRx

REF 2

REF 1

TRIG

AKTV

Actual value

(for ANF=3)

Status bit

Output

Interrupt

The actual value ”-1” is stored as final value, REF2 triggers an interrupt.

8-4

EWA 4NEB 811 6120-02a

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