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IP 240 Counting

8.2.4 Flagging with Status Bits

Status data is updated in every cycle of the module firmware on the IP.

If you want information about the status, you must call control FB 172 and parameterize

function 1 ”Read actual value, final value and status bits” ( Section 8.3.2). The CPU then

transfers the status bits from the IP to the data block (DW 18, 19 and 27).

Status bit AKTV (D 18.5) indicates whether the count has been enabled. It has the same meaning

as a set gate signal.

Status bit TRIG (D 18.4) shows whether counting has begun. The status bit is set when after a po-

sitive-going gate edge the first pulse has been acquired. TRIG is reset when the status area is read

again.

Status bit DA1 (D 18.14) indicates whether digital output D1 is set.

Status bits for the actual value

Status bit REF1 (D 19.8) indicates whether the count is less than or equal to zero. REF1 is set when

the count reaches zero, and is reset with the next positive GATE signal edge.

Status bit SG (D 19.0) indicates whether the actual value stored in data words DW 31 and 33 is

positive (SG=0) or negative (SG=1).

A ”1” value in statusbit UEBL ( D 19.1 ) indicates that the actual value is out of range (actual value

<-9,999). UEBL can trigger an interrupt. It is reset when

• the status area is read

• the interrupt request bytes are read if the overflow triggered the interrupt.

Status bits for the final value

Status bit REF2 (D 19.9)=”1” indicates that the last count was terminated with the negative GATE

signal edge and that the actual value was stored as final value of the count.

Status bit SGF (D 27.0) indicates whether the final value stored in data word DW 28 is positive

(SGF=0) or negative (SGF=1).

When ”1”, status bit UEBE (D

27.1) indicates that the final value is out of range (final value <-9,999).

When ”1”, status bit UEBS (D27.2) indicates that an old final value was overwritten by a new final

value although the old final value had not been read. UEBS can trigger an interrupt, and is reset

when the status area is read.

Note

Once they have been read, status bits TRIG, UEBL, REF2 and UEBS, as well as all

interrupt bits in the interrupt request bytes, are reset on the IP. The bits that were

set can thus be read out only once.

EWA 4NEB 811 6120-02a

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Siemens IP-Module Especificaciones Pagina 130