
Semiconductor Group 6-27
On-Chip Peripheral Components
C501
Figure 6-16
Timer 2 Auto-Reload Mode (DCEN = 1)
A logic 1 at T2EX makes timer 2 count up. The timer will overflow at FFFF
H
and set the TF2 bit.
This overflow also causes the 16-bit value in RC2H and RC2L to be reloaded into the timer
registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes timer 2 count down. Now the timer underflows when TH2 and TL2 equal
the values stored in RC2H and RC2L. The underflow sets the TF2 bit and causes FFFF
H
to be
reloaded into the timer registers. The EXF2 bit toggles whenever timer 2 overflows or underflows.
This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not
flag an interrupt.
Note: P1.1/T2EX is sampled during S5P2 of every machine cycle. The next increment/decrement
of timer 2 will be done during S3P1 in the next cycle.
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