
Device Specifications
C501
Semiconductor Group 10-8
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter Symbol Limit Values Unit
24 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 24 MHz
min. max. min. max.
RD
pulse width t
RLRH
180 – 6t
CLCL
– 70 – ns
WR
pulse width t
WLWH
180 – 6t
CLCL
– 70 – ns
Address hold after ALE
t
LLAX2
15 – t
CLCL
– 27 – ns
RD
to valid data in t
RLDV
– 118 – 5t
CLCL
– 90 ns
Data hold after RD
t
RHDX
0–0–ns
Data float after RD
t
RHDZ
–63– 2t
CLCL
– 20 ns
ALE to valid data in
t
LLDV
– 200 – 8t
CLCL
– 133 ns
Address to valid data in
t
AVDV
– 220 – 9t
CLCL
– 155 ns
ALE to WR
or RD t
LLWL
75 175 3t
CLCL
– 50 3t
CLCL
+ 50 ns
Address valid to WR
or RD t
AVWL
67 – 4t
CLCL
– 97 – ns
WR
or RD high to ALE high t
WHLH
17 67 t
CLCL
– 25 t
CLCL
+ 25 ns
Data valid to WR
transition t
QVWX
5–t
CLCL
– 37 – ns
Data setup before WR
t
QVWH
170 – 7t
CLCL
– 122 – ns
Data hold after WR
t
WHQX
15 – t
CLCL
– 27 – ns
Address float after RD
t
RLAZ
–0–0ns
Parameter Symbol Limit Values Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min. max.
Oscillator period
t
CLCL
41.7 285.7 ns
High time
t
CHCX
12 t
CLCL
– t
CLCX
ns
Low time
t
CLCX
12 t
CLCL
– t
CHCX
ns
Rise time
t
CLCH
–12ns
Fall time
t
CHCL
–12ns
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