Siemens EF 88H Series Manual de usuario descargar pdf (Pagina 36)

Semiconductor Group 6-2

On-Chip Peripheral Components

C501

Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each

of the 4 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which

will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The

Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the

CPU. The level of the port pin itself is placed on the internal bus in response to a “read-pin” signal

from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to

P3) activate the “read-latch” signal, while others activate the “read-pin” signal.

Figure 6-4

Basic Structure of a Port Circuitry

MCS01822

CLK

Port

Latch

Port

Read

Latch

Read

Write

Int. Bus

Port

Driver

Circuit

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Siemens EF 88H Series Manual de usuario Pagina 36