
Semiconductor Group 6-6
On-Chip Peripheral Components
C501
Port 0, in contrast to ports 1, 2 and 3, is considered as “true” bidirectional, because the port 0 pins
float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET
in the P0 output driver (see figure 6-7) is used only when the port is emitting 1 s during the external
memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as
output port lines are open drain lines. Writing a “1” to the port latch leaves both output FETs off and
the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as
general I/O port and has to emit logic high-level (1), external pullups are required.
Figure 6-7
Port 0 Circuitry
MCS02122
D
CLK
Bit
Latch
Q
Q
Control
Addr./Data
MUX
Read
Latch
to
Latch
Read
Pin
Write
V
CC
Int. Bus
&
Pin
Port
=1
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