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Device Specification
Semiconductor Group 7-32
A/D Converter
In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is
implemented. Its successive approximation technique provides 7
µs con-version time (f
OSC
= 16
MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The
main functional blocks are shown in figure 4.
The comparator is a fully differential comparator for a high power supply rejection ratio and very
low offset voltages. The capacitor network is binary weighted providing genuine 10-bit
resolution.
The table below shows the sample time T
S
and the conversion time T
C
, which are dependend
on f
OSC
and a new prescaler (see also Bit ADCL in SFR ADCON 1).
f
OSC
[MHz] Prescaler f
ADC
[MHz] Sample Time
T
S
[µs]
Conversion Time
(incl. sample time)
T
C
[µs]
12 ÷ 8 1.5 2.67 9.33
÷ 16 0.75 5.33 18.66
16 ÷ 8 2.0 2.0 7.0
÷ 16 1.0 4.0 14.0
18 ÷ 8 – –
÷ 16 1.125 3.55 12.4
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