Siemens EF 88H Series Manual de usuario descargar pdf (Pagina 108)

Device Specification

Semiconductor Group 7-46

Multiplication/Division Unit

This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift

and normalize features. All operations are integer operation.

The MDU consists of six registers used for operands and results and one control register.

Operation of the MDU can be divided in three phases:

Operation of the MDU

To start an operation, register MD0 to MD5 (or ARCON) must be written to in a certain se-

quence according to table 5 or 6. The order the registers are accessed determines the type of

the operation. A shift operation is started by a final write operation to register ARCON (see also

the register description).

Operation Result Remainder Execution Time

32-bit/16-bit 32-bit 16-bit 6

16-bit/16-bit 16-bit 16-bit 4

16-bit

16-bit 32-bit –4

32-bit normalize – – 6

32-bit shift left/right – – 6

1 t

= 1 µs @ 12 MHz oscillator frequency.

The maximal shift speed is 6 shifts/cycle.

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 136 137

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Siemens EF 88H Series Manual de usuario Pagina 108